Generally, a level shifter is an important component of an interface circuit for receiving a narrow-range input signal and converting the input signal into a wide-range output signal. For increasing the processing speed of an integrated circuit (IC), the integrated circuit is usually equipped with a core circuit. The core circuit has a low core voltage. For outputting the output signal from the core circuit to an external circuit outside the integrated circuit, a level shifter is used as an interface circuit to convert the low core voltage into an input/output voltage.
FIG. 1 is a schematic circuit block diagram illustrating a conventional level shifter. As shown in FIG. 1, the level shifter 100 comprises an input side logic unit 110, a latching unit 120, and an output side buffering unit 130. Basically, the input signal Sin is in the range between a core voltage Vcore and a ground voltage (0V), and the output signal Sout is in the range between an input/output voltage Vio and the ground voltage (0V). In other words, if the input signal Sin is in the low-level state (0V), the output signal Sout is in the low-level state (0V). Whereas, if the input signal Sin is in the high-level state (i.e. Sin=Vcore), the latching unit 120 performs a voltage level conversion, so that the output signal Sout is in the high-level state (i.e. Sout=Vio).
FIG. 2 is a schematic circuit diagram illustrating the detailed circuitry of the conventional level shifter. The input side logic unit 110 comprises an inverter INV1. The inverter INV1 is operated between the core voltage Vcore and the ground voltage (0V). The input terminal of the inverter INV1 receives the input signal Sin. Since all components of the input side logic unit 110 are operated between the core voltage Vcore and the ground voltage (0V), the components of the input side logic unit 110 may be implemented by thin-oxide devices.
The latching unit 120 comprises transistors P1, P2, N1, and N2. The transistors N1 and N2 are collaboratively defined as a load unit 126. The source terminal of the transistor P1 is connected to the input/output voltage Vio. The drain terminal of the transistor P1 is connected to a node a1. The gate terminal of the transistor P1 is connected to a node a2. The source terminal of the transistor P2 is connected to the input/output voltage Vio. The drain terminal of the transistor P2 is connected to the node a2. The gate terminal of the transistor P2 is connected to the node a1. The source terminal of the transistor N1 is connected to a ground terminal GND. The drain terminal of the transistor N1 is connected to the node a1. The gate terminal of the transistor N1 is connected to the output terminal of the inverter INV1. The source terminal of the transistor N2 is connected to the ground terminal GND. The drain terminal of the transistor N2 is connected to the node a2. The gate terminal of the transistor N2 receives the input signal Sin. Since all components of the latching unit 120 are operated between the input/output voltage Vio and the ground voltage (0V), the components of the latching unit 120 are all implemented by thick-oxide devices.
The output side buffering unit 130 comprises an inverter INV2. The inverter INV2 is operated between the input/output voltage Vio and the ground voltage (0V). The input terminal of the inverter INV2 is connected to the node a2. The output terminal of the inverter INV2 generates the output signal Sout. Similarly, since all components of the output side buffering unit 130 are operated between the input/output voltage Vio and the ground voltage (0V), the components of the output side buffering unit 130 are implemented by thick-oxide devices.
The operating principles of the conventional level shifter 100 will be illustrated as follows. It is assumed that the core voltage Vcore is a first high voltage level, the input/output voltage Vio is a second high voltage level, and the ground voltage is a low voltage level. If the input signal Sin has the first high voltage level, the output terminal of the inverter INV1 has the low voltage level. Meanwhile, the transistor N2 is turned on, the transistor N1 is turned off, the transistor P1 is turned on, and the transistor P2 is turned off. Consequently, the node a1 generates the second high voltage level, and the node a2 generates the low voltage level. Under this circumstance, the output signal Sout from the output terminal of the inverter INV2 has the second high voltage level.
Whereas, if the input signal Sin has the low voltage level, the output terminal of the inverter INV1 has the first high voltage level. Meanwhile, the transistor N1 is turned on, the transistor N2 is turned off, the transistor P2 is turned on, and the transistor P1 is turned off. Consequently, the node a1 generates the low voltage level, and the node a2 generates the second high voltage level. Under this circumstance, the output signal Sout from the output terminal of the inverter INV2 has the low voltage level.
Since the magnitude of the input/output voltage Vio may influence the strength of turning on/off the transistors P1 and P2, the latching speed of the latching unit 120 is also affected by the magnitude of the input/output voltage Vio. Consequently, for designing the conventional level shifter, the magnitudes of the core voltage Vcore and the input/output voltage Vio should be firstly realized, and then the size of the transistor is properly adjusted according to the magnitudes of the core voltage Vcore and the input/output voltage Vio. In such way, the level shifter can be used in a specified application.
For example, if the core voltage Vcore is 1.2V, the input/output voltage Vio is 1.8V and the input signal Sin is a clock signal with a duty cycle of 50%, the processing speed is 400 Mbps. By properly adjusting the size of the transistor, the level shifter 100 of FIG. 2 can generate the output signal Sout with a duty cycle of 50%. However, if the input/output voltage Vio of the level shifter 100 is changed to 3.3V but the other conditions are kept unchanged, since the strength of turning on/off the transistors P1 and P2 is changed, the duty cycle of the output signal Sout is changed to about 40%.
On the other hand, if the core voltage Vcore is 1.2V, the input/output voltage Vio is 3.3V and the input signal Sin is a clock signal with a duty cycle of 50%, the processing speed is 400 Mbps. By properly adjusting the size of the transistor, the level shifter 100 of FIG. 2 can generate the output signal Sout with a duty cycle of 50%. However, if the input/output voltage Vio of the level shifter 100 is changed to 1.8V but the other conditions are kept unchanged, since the strength of turning on/off the transistors P1 and P2 is changed, the duty cycle of the output signal Sout is changed to about 60%.
From the above discussions, if the input/output voltage Vio of the level shifter 100 is changed, the duty cycle of the output signal Sout is correspondingly changed. In other words, the conventional level shifter 100 fails to generate the wide-range high output voltage.
In this context, the level shifter for generating the wide-range high output voltage is a level shifter for generating an output signal Sout with the nearly unchanged duty cycle when the input/output voltage Vio is changed.
Moreover, in the double data rate (DDR) memory field and the open NAND flash interface (ONFI) field, the duty cycle of the clock signal is one of the important factors. Generally, the allowable duty cycle of the clock signal is in the range between 48% and 52%. If the duty cycle of the clock signal exceeds this allowable range, the operations of the DDR memory or the flash memory become abnormal.
Therefore, there is a need of providing a level shifter for generating an output signal Sout with the same duty cycle as the input signal Sin when the input/output voltage Vio is changed within a wide range between 1.5V and 3.3V.